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One day Workshop on Hardware Description Language
Training Schedule
| Training: | Hardware Description Language |
| Date/Time: | 31.07.2018 |
| Responsible : | Mrs.R.Rajalakshmi-AP/ECE, Ms.R.Ramakala-AP/ECE and Mr.R.Ramprakash-AP/ECE |
| Time | Session | Presentation/Description | Material | Responsible Facilitators |
| 9.00-10.30am | I | Introduction- Hardware Description Language 7 Xilinx Design entry | PPT & Verilog Codes | Mrs.R.Rajalakshmi-AP/ECE |
| 10.45-12.15pm | II | Hands on Training-Verilog HDL-Different models using verilog | PPT & Verilog Codes | Mrs.R.Rajalakshmi-AP/ECE |
| 01.30-3.00pm | III | Hands on Training-Verilog coding for combinational circuits | PPT & Verilog Codes | Ms.R.Ramakala
AP/ECE |
| 03.15-04.40pm | III | Hands on Training-Verilog coding for Sequential circuits | PPT & Verilog Codes | Mr.R.Ramprakash AP/ECE |
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